Quote:
Originally Posted by adamj12b
If you look at the HCPL-4504 datasheet, you will see that turn on of the opto is _faster_ than turn off. So while opto does delay the the gate drive signal, it _lengthens_ it (not shortens)
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The datasheet shows a gentler turn-off slope, but the effect in the circuit can go either way. The bias (in this case actual "bias resistors") is to not mistakenly turn on the MOSFET from noise. That means some (many?) designs will shorten the pulse rather than lengthen it. It just depends on how far up/down the slope you turn on/off.
We have used several different optoisolators. We started out with the cheap 2701 types, which worked fine, first time, in our initial design. We didn't really care about its performance because we knew the feedback would handle it.
Our challenge started when we upgraded to faster parts in preparation for trying a SR design. We saw both shortening and lengthening of pulses as we tried to get noise-safe, stable operation, and predictable symmetrical latency. We tried the same optoisolator that Cougar used, and didn't see any improvement. (It was actually initially worse because of a lower CTR, we needed to increase the drive and decrease the pull-up current.)
Quote:
Originally Posted by adamj12b
A PI loop controls current by controlling pulse width. This loop will set the correct PWM to make the requested current. You can make the current reference jump from zero (foot of gas) to 10A minimum or so. This approach would be far less sensitive to motor resistance and battery pack voltage than a minimum PWM type parameter.
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Which is why it's fine to eliminate narrow pulses, either on or off. The error will accumulate and be corrected.
Quote:
Originally Posted by adamj12b
In any case we wanted to avoid the behavior of the Curtis. There minimum pulse width (on time) is enforced. That resulted in jerky starts (particularly with low resistance motors) where initial current was high until some RPM was built up and the motor would generate counter EMF. The solution was to drop the switching frequency when first applying pulses. The side effect is the well known Curtis whine. This is something we wanted to avoid.
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From looking at an old analog golf cart controller, I believe that they simply halve the frequency for the low range. The result is an audible-frequency whine and poor low-speed control. It has become an endearing, familiar and comforting sound to many golfers. Perhaps not so much for us.
Once you have digital control it's easy to avoid that fixed-frequency whine. A little bit of A/D or control rounding noise is enough to make spread out the audible frequencies.
Quote:
Originally Posted by adamj12b
The PWM unit of the AVR is run in phase correct PWM mode.
From the AVR spec:
... If OCR1A is outside this range, the PWM output will not work and will be stuck in either a high or low state (undefined).
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Our controller is also using the AVR (although we are switching to the STM32), initially in mode 3 and later in mode 10.
I'll need to re-read the datasheet to see if I missed something, but we never encountered a problem. I don't believe this problem occurs if you follow the datasheet closely,
.... I just did a quick scan and found this text:
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The extreme values for the OCR2A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
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I had actually been thinking that we didn't have a problem because we always initialized to off at zero, and approached saturation from a non-zero value. Apparently there is explicit logic in the timer circuit to handle this case.
Quote:
Originally Posted by adamj12b
So we have 2/16us low. That is 125ns.
This is shorter than the delay times of the opto. I think the pulse won't even make its way to the gates of the FETs. Even if it did, the RC constant of the gate capacitances and gate resistors would not bring the gate voltages down to anywhere near the gate threshold voltage. In short, it won't switch the FETs and the output will be pure DC.
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Ah, but it does in some cases. In some of our power stages we are using 10 ohm gate resistors with low gate charge MOSFETs. A 125ns pulse is easily enough to hit the threshold and "ring the bell". (Yes, that power stage was ring prone anyway. We added 33 ohm resistors in series with the permanent gate resistors to calm it down.)
If your isolation circuit and gate drive is slower, there will still be a point where you have a short pulse that does a half switch.
The point is the same in either case. Either the short pulse doesn't get through, and you can get rid of it. Or it just generates heat, and you should get rid of it.