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The dspic has priority levels for the interrupts. 0-7. If priority(A) < priority(B), B can interrupt A, but A cannot interrupt B. I have it set so that the only thing higher than the A/D is the change notification interrupt, which is catastrophically bad if that happens(well, hardware overcurrent, which isn't so bad. haha), and you have to cycle power because the hardware has permanently disabled everything until then. So I don't think anything bad can happen. I just like to have all the stuff happen in the A/D interrupt so that I know which currents/voltages go with the FOC calculations. It could happen that outside the interrupt you use phase A current from 0.0001 seconds before, and phase B current from now, which defeats the simultaneous A/D sampling. I'm sure there's a way around it, like seeing when counter10k has incremented, but then you are having to check other stuff rather than just doing what needs to be done. My thinking was, as long as nothing bad can happen, it's OK if 99% of the time is in the A/D interrupt. The UART interrupts just have to get to the back of the bus. haha. The UART interrupts are pretty much Rosa Parks. I very much like your organizational ideas, btw. I need to be able to tear things down and try a bunch of stuff with a working copy though. Although quite a bit of stuff isn't changing, so I think it will be pretty practical for you to work on what you are talking about, and I use a copy based on something that has been reorganized.
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