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Old 10-21-2015, 02:23 PM   #2211 (permalink)
e*clipse
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I've got a pretty simple simulation going on Simplis.

The model uses ideal switches and ideal diodes as Paul suggested.

For detail, I've added resistance in the battery pack, resistance and inductance in the power wires to the controller, resistance in the bus capacitor, resistance and inductance in the motor controller bus, and resistance and inductance in the motor load. The motor is wired as a wye connection with two inputs (with ideal switches) and one output with a pair of diodes returning to the input phases. **whew**

For the resistance and inductance values, I've used parallel wire models. For the planer bus, I used PCB stacked stripline models.

With all that, and the numbers matching the best I have for the values, I've discovered a few things, but it's still not good enough. For one, I think I've found two major issues with that paper:
1) They didn't include most of the parameters I listed above. For example, power source and capacitor resistance aren't included. This is huge, because the power supply could then supply ALL the current. If the bus capacitor and all the source impedance is included, the balance of current shifts dramatically to the bus capacitor. You could think of it as two loops: source > bus capacitor and bus capacitor > load. So far I've found the balance of current depends a lot on the duty cycle. The paper is right in that the highest capacitive current load is at 50% duty cycle.

2) They seem to make the assumption that the center of the wye is at 50% of the bus voltage. My testing with the above circuit shows the neutral point much closer to the output voltage (ground in this case)

So, in this testing I've seen a number of interesting things. Of course this is just a model and I'd like to ensure it's kind of close to reality. . .
In some ways, it can be considered a model of a locked rotor test. Since this is one of the harshest tests from a motor current perspective, that's good. I tried to figure out a way to include BEMF, but it may just muddy the results.

If thingstodo, Paul, or anyone hanging around here have found different results in their real world testing. Please let me know - i'd like to make a useful model for this problem.

The interesting stuff:
1) at 50% duty cycle, the current from the bus capacitor to a phase leg can be higher than the current out of the battery.
2) There are extremely high currents circulating back through the diodes into the input phase legs. They do seem to stabilize in the transient test, but the current in the output is in this case 2X the current in the input phase legs. In other words, the current circulating in that leg can be about 2.5X the current coming from the battery!
3) If the stuff mentioned above is correct, then the model can be used for modeling "ripple current" - which is HUGE compared to the current discussed in that paper.
4) The model doesn't really have a good way of looking at transient voltage spikes - Paul have you found this to be true in your simple model? It seems one might need to use "real" FET's and diodes to see these affects.

Sooooo, I've found quite a bit ( 2X to 4X ) more capacitance than that paper recommends is needed. However, this big, low impedance capacitor (and bus system) may reduce voltage spikes significantly, reducing the voltage required for the switches and capacitor.

Thoughts anyone? Once this model is sorted, I'll post it here.

- E*clipse

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