[e*clipse]

Originally Posted by thingstodo

I split this into a couple of posts - BOY DO I GET LONG-WINDED!

That's exactly what I thought when I posted my question.

Would it simplify things a bit to model as 2 separate systems?

I don't think so. It's the inter-relatedness between the load and supply that is making this an interesting problem. I think if the two were seperated, it would require making some assumptions about the part left out. This could result in errors, like that paper.

I put an X beside the parts that I think can be ignored for simplicity. The resistances and inductances should be really small?

Ideal Battery -> series resistance ->
ideal wire series resistance -> Xseries inductance ->
ideal capacitor series resistance -> parallel capacitance ->
ideal wire Xseries resistance -> Xseries inductance ->
Ideal battery

One of the interesting things I've found regarding the battery with all the resistance and line inductance thrown in - the current out of the battery is sinusoidal. That could have an effect on the capacitor fill rate, for example. BTW, the inductance and resistance I'm using for the battery are based on 00 wire running for about 3 meters. I'm assumming a worst case of batteries in trunk, front motor controller/motor. The battery resistance was taken from an ORNL test of a Nissan Leaf battery pack.

Set up the peak to peak or ripple voltage that is acceptable and find out the capacitance required if you 'take all of that energy out of the capacitor' as a step change

This is where it gets pretty dynamic, depending on the combination of switching frequency, capacitance, and duty cycle. We could eliminate one variable by looking only at the worst case, 50% duty cycle. However, switching frequency has a large affect on capacitor size. Just like boost converters, faster >> smaller inductor.

Then the second circuit is a bit simpler

Ideal capacitor -> series resistance ->
ideal wire series resistance -> Xseries inductance ->
ideal motor series resistance -> series inductance ->
ideal wire series resistance -> Xseries inductance ->
Ideal capacitor

Here's where we're delving into stuff that causes the "traditional" methods fall short. SBE has quite a bit of stuff about reducing the bus inductance for best performance. Basically, the extremely low ESR of the capacitor opens an opportunity to further reduce other stuff. The other stuff, like bus inductance, is actually now relatively important because the other factors have been significantly reduced.

As you've stated, bus inductance has little/no affect on the current that the bus capacitor sees, because it is so small. Thus, a model to find the current rating of the capacitor doesn't need this detail. However it can lead to a significant turn-off spike, requiring higher voltage rating capacitors and switches.

The same peak to peak or ripple voltage (I think a triangular wave source added to the ideal capacitor may have worked ... this was 25 years ago in university so I'm a bit fuzzy) on the capacitor should illustrate the differences in the controller side as the ripple voltage is higher or lower.

In my uninformed opinion (OK - guess!), the worst case for capacitance should be when the triangular wave is at it's minimum (from the battery source) and the controller still needs to send a maximum duty cycle pulse to the motor?

I guess I don't see accuracy of a triangle wave source. I think that was a good approximation back when inverters were running really slow and electrolytic capacitors were the only choice.

I did see a triangular voltage at the capacitor if I matched the capacitor to the load current well. If the capacitor is undersized, those waveforms look more like an ocean wave, with a curve near the end of the fill/empty. The current waveforms into the capacitor are very funky; they are sort of a step function, with an asymmetrical top and bottom.

Please - I'm - not downplaying this contribution. I really really appreciate it; it's definitely making me think more about this. Thank you!

At this point it looks like one SBE ring cap will do the job; it doesn't need parallel capacitors. Since the capacitors all have extremely low ESR - about 2 or 3 mOhms at 5>100khz, I'm just using 2.5mOhms for all the capacitor ESR values in various tests.

For the bus/capacitor inductance, I'm using values in the range of 5nH > 20nH, based on SBE tests with capacitors and a planer bus. Believe it or not, little details like the shape of a cut-out can significantly effect the current density at high frequencies. Fun stuff!

Thanks again,
E*clipse