Quote:
Originally Posted by msc
VSS input may miss pulses that are two short.
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Yeah, that makes sense to me. I was thinking earlier that it's like the VSS routine is missing pulses - pulses are starting and ending before the routine gets called. That would happen at very high frequencies if you were feeding it a plain square wave. Since this circuit outputs short pulses, it's easier for the guino's VSS routine to miss the detection window.
Quote:
Originally Posted by msc
A wide range of logic gates could also be used for level matching if that's what you have laying around.
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A flip-flop would be perfect with that frequency doubling circuit. Wire it up to toggle on each clock rising edge, then feed your circuit's output to the clock pin. The flip-flop will act as a frequency divider, so you'll get the proper number of pulses out in a nice 50% duty cycle square wave.