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Old 07-26-2011, 04:05 PM   #51 (permalink)
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that's great for the bottom diodes, what will you do for the top ones? I can't see an easy way of doing that with this chip.

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Old 07-26-2011, 06:49 PM   #52 (permalink)
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that's great for the bottom diodes, what will you do for the top ones? I can't see an easy way of doing that with this chip.
I was going to use a charge pump circuit to provide the power and swap the D and VSS. (it works in simulation with some glitches)

the other option would be the LM5050-2 chip
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Old 07-27-2011, 03:35 AM   #53 (permalink)
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the top fets need to be P-channel, and the drive needs to be inverted. you can use N-channel, but then you need common drains, not sources?
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Old 07-27-2011, 03:36 AM   #54 (permalink)
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Have you looked at those IR chips I posted the link on?
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Old 07-27-2011, 05:34 PM   #55 (permalink)
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the top fets need to be P-channel, and the drive needs to be inverted. you can use N-channel, but then you need common drains, not sources?
As you noted, you can use all N channel you just need to drive the gate voltage higher than what your getting in. With my charge pump circuit I can do it. Doing all N channel fets provides an advantage as they have lower on resistance.

I did look at the IR parts. I like the Linear parts more though. The national part might be the best of the lot but I can't get a simulation model of it to work.

I have a working simulation with the linear part in LTspice. It does have problems that appear to be artificial (won't let me simulate ff all fets are the same, Glitch spikes and ringing). Other than than it works quite well.

I can send it to you if you like. (it is a bit messy)
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Old 07-28-2011, 03:41 AM   #56 (permalink)
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that would be great thanks, I use simetrix mainly, but it's not much of a problem to re-install LTspice. could you zip it up with the model as well please? Are you using one chip for both negative fets and one for each of the upper ones? well, I guess I will see in the sim.
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Old 07-28-2011, 02:33 PM   #57 (permalink)
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I will need you to message me your email address.

Actually in order to get the turn on time for the fets fast enough for an alternator spin 18000 rpm I have ganged two chips per fet. It took some careful reading of the data sheets, app notes, and articles to figure out if this was okay to do but it is.

I it looks like I broke the simulation tinkering with it. I'll play with it until I get it working again.

I have two separate circuits. One is the test circuit and the other is a reference to how they rectify alternators now. Changing one can effect the simulation output of the other even though they are totally isolated. I haven't figured out why yet but I think its due to the time step.
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Old 08-01-2011, 06:22 PM   #58 (permalink)
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I guess I need to start looking at FETs. I think the requirements will be an Rds on resistance of 6 miliOhms or less and a gate charge of 40nC or less. maximum IDS has to be 40A or more. Vds has to be 40 or more.
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Old 08-01-2011, 08:18 PM   #59 (permalink)
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here is a picture of the out put I'm getting showing the voltage difference between the active vs passive rectification. (Note this is for the same voltage input and not the same power input.)
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Old 08-11-2011, 05:03 PM   #60 (permalink)
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Has any one worked on this any more? As for the fan that could be improved with a lighter version maybe plastic but for added cooling the body of the alt could be painted with VHT wrinkle paint or krylon wrinkle it will increase the surface area and help it cool.

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